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AN1044/1098 1/12 application note multiple interrupt sources management for st7 mcus by microcontroller division application team introduction the goal of this application note is to present a technique for managing several external i/o in- terrupts with a member of the st7 series of mcus (here a st72251). 1 i/o cell structure each pin of the microcontroller i/o port can be programmed independently as digital input (with or without interrupt generation) or digital output. some have also alternate function (spi, sci, timers...). if you want to change the i/o port configuration, take care to respect the state transition diagram (please, refer to the datasheet for more details). figure 1 . i/o block diagram dr ddr latch latch data bus dr sel ddr sel v dd pa d analog switch analog enable (adc) m u x alternate alternate alternate enable common analog rail alternate m u x alternate input pull-up (s ee t able below ) output p-buffer (s ee t able b elow ) n-buffer 1 0 1 0 or latch or sel from other bits external pull-up condition enable enable gnd (s ee t able below ) (s ee n ote below ) cmos schmitt trigger source (eix) interrupt polarity sel 1
interrupt generation 2/12 2 interrupt generation when you use several pins as interrupt pull up inputs, problems may occur if more than one input generates an interrupt within the same period of time. some will be masked, and then wont be taken into account. all pins configured as external interrupt mode are connected together in a logical nand function to the same core interrupt vector (see figure 1). an external interrupt is an edge and/ or a low level applied on a pin configured as an input with pull up and interrupt. to get a high level at the interrupt line, all interrupt pins must be high. the sensitivity chosen for interrupts in our application is falling edge (please, refer to the mis- cellaneous register). lets take a look on the possible problem: as we can see, some interrupts may be inhibited by others if the software doesnt prevent such events. its because of the logical nand performed in the chip that the interrupt vector wont be able to treat a nested interrupt. this application note presents then a solution in order to detect and to treat all falling edges of potential interrupt pins. 3 detecting interrupts the interrupts edge or level sensitivity has to be programmed by software using the miscella- neous register. in this application note, we then chose falling edge. we use the port c (pc0 to pc4) as input with pull-up and interrupt (external interrupt 1). to configure it correctly, please refer to the datasheet. we use pa0 as output to apply on port c pins a low level to create an interrupt. pin 1 pin 2 interrupt signal to the interrupt controller
3/12 detecting interrupts the main point of the technique used here consists on enabling and disabling inputs which are potential sources of interrupt. once an interrupt is detected (its falling edge), its automatically treated (the main program goes to the interrupt subroutine) and then disabled. if another inter- rupt occurs, all pins are tested (if the or register bit is set, the interrupt is enabled) in order to see a falling edge which hasnt been treated yet. once a high level is detected (by polling) on a pin which previously generated an interrupt, the interrupt mode is enabled once again (set- ting or bit). you can have a different interrupt subroutine depending on the pin responsible of the interrupt. when using this technique, the user is able to detect every single falling edge interrupt with no risk of overlapping between them. the interrupt subroutine must test every pin and make the right relative jump to the interrupt procedure according to the pin which generated the interrupt. pin 1 pin 2 pin 1 interrupt mode disabled mode disabled pin 2 interrupt pin 1 interrupt mode enabled pin 2 interrupt mode enabled :enable interrupt or=1 :disable interrupt or=0 interrupt signal interrupts detection to the core
flowcharts 4/12 4 flowcharts figure 1. polling subroutine n is the number of pins able to generate an interrupt. begin polling on pin0 pin0=1 or0=1? set or0 yes no polling on pin n no orn=1? set orn users program yes pin n=1
5/12 flowcharts figure 2. interrupt subroutine n still represents the number of pins able to generate an interrupt. in the main program, port c pins are tested to be enabled and the led corresponding to the last pin which caused the interrupt toggles until another interrupt occurs. or0=0? reset or0 dr0=0? no yes yes orn=0? yes yes reset orn drn=0? no iret yes int specific routine for pin n, here setting of pbn. iret int specific routine for pin0, here iret setting of pb0. process0 no no processn
software 6/12 5 software the assembly code given below is guidance only. the complete software with all the files can be found in the software library. st7/ ; the first line is reserved ; for specifying the instruction set ; of the target processor ;************************************************************************ ; title: softit.asm ; author: ppg microcontroller applications team ; description: main program (use of the halt mode for decoding ;a keypad). ; ;************************************************************************ title softit.asm ; this title will appear on each ; page of the listing file motorola ; this directive forces the motorola ; format for the assembly (default) #include st72251.inc ; include st72251 registers and memory mapping file #include constant.inc ; include general constants file ;*********************************************************************** ; variables, constants defined and referenced locally ; you can define your own values for a local reference here ;*********************************************************************** ;************************************************************************ ; public routines (defined here) ;************************************************************************ words segment rom ;************************************************************************ ; initializations routines ;************************************************************************ .init ld a,#80 ld miscr ,a ; falling edge sensitive , normal mode. ld a,#$1f ld pcor,a ; port c defined as input with pull up clr a ld pcddr,a ; and interrupt (pc0 to pc4).
7/12 software ld a,#$3f ld pbddr,a ; portb defined as output push-pull ld pbor,a ; (to make corresponding leds toggle). bset paddr,#0 bres paor,#0 ; pa0 defined as output (source of the it). ret ;************************************************************************ ; tempo routine ;************************************************************************ .delay ; waiting loop of 45ms for fcpu=8mhz. ld y,#200 loop2 ld x,#$ff loop1 dec x jrne loop1 dec y jrne loop2 ret ;************************************************************************ ; macro routine to enable interrupts on the considered pin. ;************************************************************************ enable_it macro num,label btjt pcor,#num,label ;if pcnum is in it mode, jump to label bset pcor,#num ;else end of it and pcnum interrupt enable. jra label mend ;********************************************************** ; program code ;********************************************************** .main call init rim ; enable interrupts. loop bset padr,#0 btjt pcdr,#0,enb0 ; enable pcx if previous it is over. .go0 btjt pcdr,#1,enb1
software 8/12 .go1 btjt pcdr,#2,enb2 .go2 btjt pcdr,#3,enb3 .go3 btjt pcdr,#4,enb4 .go4 ld a,pbdr clr pbdr call delay ld pbdr,a ; toggling of pbx(ledx), responsible of the it. call delay clr pbdr call delay ld pbdr,a call delay bres padr,#0 ; falling edge and low level (pa0=0). call delay jra loop ; infinite loop, wait an interrupt occurs. .enb0 enable_it 0,go0 .enb1 enable_it 1,go1 .enb2 enable_it 2,go2 .enb3 enable_it 3,go3 .enb4 enable_it 4,go4 .enb5 enable_it 5,go5 ; ***************************************************************** ; this set of instructions uses simple assembly mnemoniques. ; we can notice that the loop label is defined only locally (no dot ; in front of it) so it can not be seen by others modules linked ; with this file. ; ***************************************************************** ; ******************************************** ; * * ; * interrupt sub-routines library section *
9/12 software ; * * ; ******************************************** .dummy iret .sw_rt jp main ; empty subroutine. go back to main (iret instruction) .ext0_rt iret .ext1_rt btjt pcor,#0,it0 ; if or=0, pin disabled (floating input). p1 btjt pcor,#1,it1 ; if or=1 -> interrupt subroutine. p2 btjt pcor,#2,it2 p3 btjt pcor,#3,it3 p4 btjt pcor,#4,it4 .return iret .it0 btjt pcdr,#0,p1 ; if no low level on the pin -> no it. bres pcor,#0 ; if it -> disable the pin. jra process0 ; it process. .it1 btjt pcdr,#1,p2 bres pcor,#1 jra process1 .it2 btjt pcdr,#2,p3 bres pcor,#2 jra process2 .it3 btjt pcdr,#3,p4 bres pcor,#3 jra process3 .it4 btjt pcdr,#4,return bres pcor,#4 jra process4 .process0 clr pbdr ; clear leds.
software 10/12 bset pbdr,#0 ; set the led corresponding to the pin responsible of iret ; the it. .process1 clr pbdr bset pbdr,#1 iret .process2 clr pbdr bset pbdr,#2 iret .process3 clr pbdr bset pbdr,#3 iret .process4 clr pbdr bset pbdr,#4 iret .spi_rt iret .tima_rt iret .timb_rt iret .i2c_rt iret segment vectit ; ******************************************************************* ; this last segment should always be there in your own programs. ; it defines the interrupt vector adresses and the interrupt routines labels ; considering the microcontroller you are using. ; refer to the mcus datasheet to see the number of interrupt vector ; used and their addresses. ; remind that this example is made for a st72251 based application. ; ******************************************************************* ; *******************************************************************
11/12 software ; each interrupt vector uses two addresses in rom, thats what the directive ; dc.w means. it says reserve a word location (.w) in rom (dc) and code ; the routines label in those two addresses. ; yet, when an interrupt occurs, for example from the timerb, timerbs routine ; address (timb_rt) will be loaded in the pc and the program will jump to this ; label if allowed. it will execute this routine and then will go back to the main ; program (see interrupt chapter in the datasheet for a more precise description ; of how to handle interrupts in st72 micros). ; ******************************************************************* dc.w dummy ;ffe0-ffe1h location dc.w dummy ;ffe2-ffe3h location .i2c_it dc.w i2c_rt ;ffe4-ffe5h location dc.w dummy ;ffe6-ffe7h location dc.w dummy ;ffe8-ffe9h location dc.w dummy ;ffea-ffebh location dc.w dummy ;ffec-ffedh location .timb_it dc.w timb_rt ;ffee-ffefh location dc.w dummy ;fff0-fff1h location .tima_it dc.w tima_rt ;fff2-fff3h location .spi_it dc.w spi_rt ;fff4-fff5h location dc.w dummy ;fff6-fff7h location .ext1_it dc.w ext1_rt ;fff8-fff9h location .ext0_it dc.w ext0_rt ;fffa-fffbh location .softit dc.w sw_rt ;fffc-fffdh location .reset dc.w main ;fffe-ffffh location end ; be aware of the fact that the end directive should not ; stand on the left of the page like the labelss names.
software 12/12 "the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connexion with their products." information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com

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